 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Si5023 MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMPLIFIER Features High-speed clock and data recovery device with integrated limiting amp: Supports OC-48/12/3, STM-16/4/ Bit error rate alarm 1, Gigabit Ethernet, and 2.7 Gbps Reference and referenceless FEC operation supported (R) Loss-of-signal level alarm DSPLL technology Data slicing level control Jitter generation 3.0 mUIrms 10 mVPP differential sensitivity (TYP) Small footprint: 5 x 5 mm 3.3 V supply Ordering Information: See page 25. Applications SONET/SDH/ATM routers Add/drop multiplexers Digital cross connects Gigabit Ethernet interfaces SONET/SDH test equipment Optical transceiver modules SONET/SDH regenerators Board level serial links Pin Assignments Si5023 BER_ALM CLKOUT+ 23 Description RATESEL0 1 2 3 4 5 6 7 28 27 26 25 24 CLKOUT- 22 21 20 19 CLKDSBL BERMON BER_LVL VDD VDD REXT RESET/CAL VDD DOUT+ DOUT- GND The Si5023 is a fully-integrated, high-performance limiting amp and clock and data recovery (CDR) IC for high-speed serial communication systems. It derives timing information and data from a serial input at OC-48/12/3, STM-16/4/1, or Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data streams is also provided for OC-48/STM-16 applications that employ forward error correction (FEC). Use of an external reference clock is optional. Silicon Laboratories DSPLL(R) technology eliminates sensitive noise entry points, thus making the PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance. The Si5023 represents a new standard in low jitter, low power, small size, and integration for high-speed LA/CDRs. It operates from a 3.3 V supply over the industrial temperature range (-40 to 85 C). RATESEL1 LOS_LVL SLICE_LVL REFCLK+ REFCLK- LOL GND Pad 18 17 16 15 8 9 10 11 12 13 14 LOS DIN+ DIN- VDD Top View Functional Block Diagram LOS_LVL LOS Signal Detect Retimer DSQLCH BUF 2 DOUT+ DOUT- DIN+ DIN- 2 Limiting Amp DSPLL BER Monitor BUF 2 CLKOUT+ CLKOUT- CLK_DSBL REFCLK+ REFCLK- (Optional) 2 Lock Detection 2 Bias Gen. Reset/ Calibration BER_ALM REXT BERMON SLICE_LVL LTR BER_LVL LOL RATESEL RESET/CAL Rev. 1.3 6/08 Copyright (c) 2008 by Silicon Laboratories DSQLCH VDD LTR Si5023 Si5023 2 Rev. 1.3 Si5023 TABLE O F CONTENTS Section Page 1. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1. Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.2. DSPLL(R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.3. Multi-Rate Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.4. Operation Without an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5. Operation With an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.6. Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.7. Lock-to-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.8. Loss-of-Signal (LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.9. Bit Error Rate (BER) Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.10. Data Slicing Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.11. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.12. RESET/DSPLL Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.13. Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.14. Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.15. Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.16. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.17. Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.18. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.19. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5. Pin Descriptions: Si5023 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7. Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Rev. 1.3 3 Si5023 1. Detailed Block Diagram LOS BER_LVL BER_ALM BERMON RATESEL[0:1] LTR DSQLCH LOS_LVL Signal Detect BER Monitor Retime DOUT+ DOUT- DIN+ Limiting Amp Phase Detector A/D DSP n VCO CLK Dividers CLKOUT+ CLKOUT- DIN+ SLICE_LVL Slicing Control Lock Detection CLKDSBL REFCLK (optional) Bias Generation LOL REXT Calibration RESET/CAL 4 Rev. 1.3 Si5023 2. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Temperature Si5023 Supply Voltage2 Symbol TA VDD Test Condition Min1 -40 3.135 Typ 25 3.3 Max1 85 3.465 Unit C V Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 C unless otherwise stated. 2. The Si5023 specifications are guaranteed when using the recommended application circuit (including component tolerance) of "3. Typical Application Schematic" on page 11. V SIG NAL+ SIG NAL- V IS t A. Operation with Single-Ended Inputs V SIGNAL+ SIGNAL- 0.5 V ID (SIGNAL+) - (SIG NAL-) V ID t B. O peration with Differential Inputs and Outputs Figure 1. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT) t Cf-D DOUT t C r-D CLK OUT Figure 2. Clock to Data Timing Rev. 1.3 5 Si5023 DO UT, CLKO UT tF tR 80% 20% Figure 3. DOUT and CLKOUT Rise/Fall Times taq RESET/Cal LOL DATAIN LOL taq Figure 4. PLL Acquisition Time DATAIN LOS Threshold Level LOS tLOS Figure 5. LOS Response Time 6 Rev. 1.3 Si5023 Table 2. DC Characteristics (VDD = 3.3 V 5%, TA = -40 to 85 C) Parameter Supply Current FEC (2.7 GHz) OC-48 GbE OC-12 OC-3 1 Symbol Test Condition IDD Min -- -- -- -- -- Typ 173 170 175 180 190 571 561 577 594 627 1.50 2.10 -- -- -- -- 100 800 800 1.80 100 -- -- -- -- -- 100 -- -- Max 184 180 185 190 197 637 623 640 657 682 1.62 2.30 500 1000 750 1500 116 1000 1100 2.35 116 .8 -- 10 10 -- 125 0.4 -- Unit mA Power Dissipation FEC (2.7 GHz) OC-48 GbE OC-12 OC-3 Common Mode Input Voltage (DIN)2 Common Mode Input Voltage (REFCLK) DIN Single-ended Input Voltage Swing2 2 2 2 PD VDD = 3.3 V (5%) -- -- -- -- -- 1.30 1.90 10 10 200 200 84 700 700 1.60 84 -- 2.0 -- -- 9 50 mW VICM VICM VIS VID VIS VID RIN VOD VOD VOCM ROUT VIL VIH IIL IIH RIN RIN VOL VOH See Figure 17 See Figure 16 See Figure 1A See Figure 1B See Figure 1A See Figure 1B Line-to-Line 100 Load Line-to-Line 100 Load Line-to-Line 100 Load Line-to-Line Single-ended V V mV mV mV mV mVPP mVPP V V V A A k k V V DIN Differential Input Voltage Swing REFCLK Differential Input Voltage Input Impedance (DIN) Differential Output Voltage Swing (DOUT) Differential Output Voltage Swing (CLKOUT) Output Common Mode Voltage (DOUT,CLKOUT) REFCLK Single-ended Input Voltage Swing Swing2 Output Impedance (DOUT,CLKOUT) Input Voltage Low (LVTTL Inputs) Input Voltage High (LVTTL Inputs) Input Low Current (LVTTL Inputs) Input High Current (LVTTL Inputs) Input Impedance (LVTTL Inputs) LOS_LVL, BER_LVL, SLICE_LVL Input Impedance Output Voltage Low (LVTTL Outputs) Output Voltage High (LVTTL Outputs) IO = 2 mA IO = 2 mA -- 2.0 Notes: 1. No load on LVTTL outputs. 2. These inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input must be ac coupled to ground. Rev. 1.3 7 Si5023 Table 3. AC Characteristics (Clock and Data) (VDD = 3.3 V 5%, TA = -40 to 85 C) Parameter Symbol Test Condition RATESEL[0:1] = 11 RATESEL[0:1] = 01 RATESEL[0:1] = 10 RATESEL[0:1] = 00 Figure 3 on page 6 Figure 3 on page 6 Min 2.46 1.232 616 154 -- -- 47 Typ -- -- -- -- 70 70 50 80 80 230 230 490 860 4100 -40 -30 -- -- Max 2.7 1.35 675 158 90 90 53 110 110 265 265 560 940 4200 -10 0 -- -- Unit GHz GHz MHz MHz ps ps % of UI ps ps ps Output Clock Rate fCLK Output Clock Rise Time--OC-48 Output Clock Fall Time--OC-48 Output Clock Duty Cycle OC-48/12/3 Output Data Rise Time--OC-48 Output Data Fall Time--OC-48 Clock-to-Data Delay FEC (2.7 GHz) OC-48 GbE OC-12 OC-3 Clock to Data Delay FEC (2.7 GHz) OC-48 Input Return Loss Slicing Level Offset (relative to the internally set input common mode voltage) Loss-of-Signal Range* (peak-to-peak differential) Loss-of-Signal Response Time tR tF tR tF tCr-D Figure 3 on page 6 Figure 3 on page 6 Figure 2 on page 5 -- -- 190 190 440 800 4000 tCf-D Figure 2 on page 5 -70 -60 100 kHz-1.5 GHz 1.5 GHz-4.0 GHz -15 -10 ps dB dB VSLICE SLICE_LVL = 750 mV to 2.25 V LOS_LVL = 1.50 TO 2.50 V Figure 5 on page 6 0 8 See Figures 12 and 13. VLOS tLOS -- 20 40 25 mV s *Note: Adjustment voltage is calculated as follows: VLOS = (LOS_LVL - 1.50)/25. 8 Rev. 1.3 Si5023 Table 4. AC Characteristics (PLL Characteristics) (VDD = 3.3 V 5%, TA = -40 to 85 C) Parameter Jitter Tolerance (OC-48)* Symbol JTOL(PP) Test Condition f = 600 Hz f = 6000 Hz f = 100 kHz f = 1 MHz f = 30 Hz f = 300 Hz f = 25 kHz f = 250 kHz f = 30 Hz f = 300 Hz f = 6.5 kHz f = 65 kHz IEEE 802.3z Clause 38.6.8 Min 40 4 3 0.3 60 6 4 0.4 60 6 4 0.4 600 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- Unit UIPP UIPP UIPP UIPP UIPP UIPP UIPP UIPP UIPP UIPP UIPP UIPP ps Jitter Tolerance (OC-12 Mode)* JTOL(PP) Jitter Tolerance (OC-3 Mode)* JTOL(PP) Jitter Tolerance (Gigabit Ethernet) Receive Data Total Jitter Tolerance Jitter Tolerance (Gigabit Ethernet) Receive Data Deterministic Jitter Tolerance RMS Jitter Generation* Peak-to-Peak Jitter Generation Jitter Transfer Bandwidth * * TJT(PP) DJT(PP) IEEE 802.3z Clause 38.6.9 370 -- -- ps JGEN(RMS) with no jitter on serial data JGEN(PP) JBW with no jitter on serial data OC-48 Mode OC-12 Mode OC-3 Mode -- -- -- -- -- -- -- 20 -- 1.5 -- 3.0 25 -- -- -- 0.03 1.6 100 2.0 2.5 155.52 77.76 19.44 -- 650 5.0 55 2.0 500 130 0.1 2.2 500 5.5 5.5 -- mUI mUI MHz kHz kHz dB ms s ms ms MHz Jitter Transfer Peaking Acquisition Time--OC-48 (Reference clock applied) * JP TAQ Acquisition Time--OC-48 (Reference-less operation) TAQ Reference Clock Range After falling edge of RESET/CAL From the return of valid data After falling edge of RESET/CAL From the return of valid data See Table 8 on page 13 Input Reference Clock Frequency Tolerance Frequency Difference at which Receive PLL goes out of Lock (REFCLK compared to the divided down VCO clock) CTOL -500 -- 500 -- ppm ppm *Note: As defined in Bellcore specifications: GR-253-CORE, Issue 3, September 2000. Using PRBS 223 - 1 data pattern. Rev. 1.3 9 Si5023 Table 5. Absolute Maximum Ratings Parameter DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pf, 1.5 k) TJCT TSTG Symbol VDD VDIG VDIF Value -0.5 to 3.5 -0.3 to 3.6 -0.3 to (VDD+ 0.3) 50 -55 to 150 -55 to 150 1 Unit V V V mA C C kV Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Symbol JA Test Condition Still Air Value 38 Unit C/W 10 Rev. 1.3 Si5023 3. Typical Application Schematic LVTTL Control Inputs BER Alarm Loss-of-Signal Indicator Indicator Loss-of-Lock Indicator BER Monitor 2 LTR CLKDSBL RATESEL1-0 RESET/CAL BER_ALM DSQLCH LOS LOL BERMON 5 kW (Optional. See Table 9) High Speed Serial Input DIN+ DIN- Si5023 DOUT+ DOUT- Recovered Data SLICE_LVL System Reference Clock (Optional) REFCLK+ REFCLK- LOS_LVL BER_LVL CLKOUT+ CLKOUT- Recovered Clock REXT VDD 100 pF x (4) VDD 10 k (1%) 0.1 mF Loss-of-Signal Level Set Data Slice Level Set Bit Error Rate Level Set Rev. 1.3 GND 11 Si5023 4. Functional Description The Si5023 integrates a high-speed limiting amplifier (LA) with a multi-rate clock and data recovery unit (CDR) that operates up to 2.7 Gbps. No external reference clock is required for clock and data recovery. The limiting amplifier magnifies low-level input data signals from a TIA so that accurate clock and data recovery can be performed. The CDR uses Silicon Laboratories DSPLL(R) technology to recover a clock synchronous to the input data stream. The recovered clock is used to retime the incoming data, and both are output synchronously via current-mode logic (CML) drivers. Silicon Laboratories' DSPLL technology ensures superior jitter performance while eliminating the need for external loop filter components found in traditional phase-locked loop (PLL) implementations. The limiting amplifier includes a control input for adjusting the data slicing level and provides a loss-ofsignal level alarm output. The CDR includes a bit error rate performance monitor which signals a high bit error rate condition (associated with excessive incoming jitter) relative to an externally adjustable bit error rate threshold. The option of a reference clock minimizes the CDR acquisition time and provides a stable reference for maintaining the output clock when locking to reference is desired. DSPLL enables clock and data recovery with far less jitter than is generated using traditional methods and it eliminates performance degradation caused by external component aging. In addition, because external loop filter components are not required, sensitive noise entry points are eliminated, thus making the DSPLL less susceptible to board-level noise sources and making SONET/SDH jitter compliance easier to attain in the application. 4.3. Multi-Rate Operation The Si5023 supports clock and data recovery for OC-48 and STM-16 data streams. In addition, the PLL was designed to operate at data rates up to 2.7 Gbps to support OC-48/STM-16 applications that employ FEC. Multi-rate operation is achieved by configuring the device to divide down the output of the VCO to the desired data rate. The divide factor is configured by the RATESEL[0:1] pins. The RATESEL[0:1] configuration and associated data rates are given in Table 7. Table 7. Multi-Rate Configuration RATESEL [0:1] 11 01 10 00 SONET/ SDH 2.488 Gbps 1.244 Gbps 622.08 Mbps 155.52 Mbps Gigabit Ethernet -- 1.25 Gbps -- -- OC-48 with 15/14 FEC 2.67 Gbps -- -- -- CLK Divider 1 2 4 16 4.1. Limiting Amplifier The limiting amplifier accepts the low-level signal output from a transimpedance amplifier (TIA). The low-level signal is amplified to a usable level for the clock and data recovery unit. The minimum input swing requirement is specified in Table 2. Larger input amplitudes (up to the maximum input swing specified in Table 2) are accommodated without degradation of performance. The limiting amplifier ensures optimal data slicing by using a digital dc offset cancellation technique to remove any dc bias introduced by the internal amplification stage. 4.4. Operation Without an External Reference The Si5023 can perform clock and data recovery without an external reference clock. Tying the REFCLK+ input to VDD and REFCLK- to GND configures the device to operate without an external reference clock. Clock recovery is achieved by monitoring the timing quality of the incoming data relative to the VCO frequency. Lock is maintained by continuously monitoring the incoming data timing quality and adjusting the VCO accordingly. Details of the lock detection and the lock-to-reference functions while in this mode are described in their respective sections below. Note: Without an external reference, the acquisition of data is dependent solely on the data itself and typically requires more time to acquire lock than when a reference is applied. 4.2. DSPLL(R) The Si5023 PLL structure (shown in Figure 1 on page 5) utilizes Silicon Laboratories' DSPLL technology to maintain superior jitter performance while eliminating the need for external loop filter components found in traditional PLL implementations. This is achieved by using a digital signal processing (DSP) algorithm to replace the loop filter commonly found in analog PLL designs. This algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage-controlled oscillator (VCO). 12 Rev. 1.3 Si5023 4.5. Operation With an External Reference The Si5023 device's optional external reference clock centers the DSPLL, minimizes the acquisition time, and maintains a stable output clock (CLKOUT) when lockto-reference (LTR) is asserted. When the reference clock is present, the Si5023 will use the reference clock to center the VCO output frequency so that clock and data can be recovered from the input data stream. The device will self configure for operation with one of three reference clock frequencies. This eliminates the need to externally configure the device to operate with a particular reference clock. The reference clock centers the VCO for a nominal output between 2.5 and 2.7 GHz. The VCO frequency is centered at 16, 32, or 128 times the reference clock frequency. Detection circuitry continuously monitors the reference clock input to determine whether the device should be configured for a reference clock that is 1/16, 1/32, or 1/128 the nominal VCO output. Approximate reference clock frequencies for some target applications are given in Table 8. out-of-lock condition, even if the data is removed from inputs. In applications requiring a more stable output clock during out-of-lock conditions, the lock-to-reference (LTR) input can be used to force the PLL to lock to the externally supplied reference. In the absence of an external reference, the lock detect circuitry uses a data quality measure to determine when frequency lock has been lost with the incoming data stream. During reacquisition, CLKOUT may vary by approximately 10% from the nominal data rate. 4.7. Lock-to-Reference The lock-to-reference input (LTR) can be used to force a stable output clock when an alarm condition, such as LOS, exists. In typical applications, the LOS output would be tied to the LTR input to force a stable output clock when the input data signal is lost. When LTR is asserted, the DSPLL is prevented from acquiring the data signal present on DIN. The operation of the LTR control input depends on which reference clocking mode is used. When an external reference clock is present, assertion of LTR will force the DSPLL to lock CLKOUT to the provided reference. If no external reference clock is used, LTR will force the DSPLL to hold the digital frequency control input to the VCO at the last value. This produces an output clock that is stable as long as supply and temperature are constant. Table 8. Typical REFCLK Frequencies SONET/SDH 19.44 MHz 77.76 MHz Gigabit Ethernet 19.53 MHz 78.125 MHz SONET/ SDH with 15/14 FEC 20.83 MHz 83.31 MHz Ratio of VCO to REFCLK 128 32 16 155.52 MHz 156.25 MHz 4.8. Loss-of-Signal (LOS) The Si5023 indicates a loss-of-signal condition on the LOS output pin when the input peak-to-peak signal level on DIN falls below an externally-controlled threshold. The LOS threshold range is specified in Table 3 on page 8 and is set by applying a voltage on the LOS_LVL pin. The graph shown in Figure 6 illustrates the LOS_LVL mapping to the LOS threshold. The LOS output is asserted when the input signal drops below the programmed peak-to-peak value. If desired, the LOS function may be disabled by grounding LOS_LVL or by adjusting LOS_LVL to be less than 1 V. Note: The LOS circuit is designed to only work with pseudorandom, dc-balanced data. 4.6. Lock Detect The Si5023 provides lock-detect circuitry that indicates whether the PLL has achieved frequency lock with the incoming data. The operation of the lock-detector depends on the reference clock option used. When an external reference clock is provided, the circuit compares the frequency of a divided-down version of the recovered clock with the frequency of the applied reference clock (REFCLK). If the recovered clock frequency deviates from that of the reference clock by the amount specified in Table 4 on page 9, the PLL is declared out of lock, and the loss-of-lock (LOL) pin is asserted. In this state, the PLL will periodically try to reacquire lock with the incoming data stream. During reacquisition, the recovered clock frequency (CLKOUT) drifts over a 600 ppm range relative to the applied reference clock, and the LOL output alarm may toggle until the PLL has reacquired frequency lock. Due to the low noise and stability of the DSPLL, there is the possibility that the PLL will not drift enough to render an In many applications, it is desirable to produce a fixed amount of signal hysteresis for an alarm indicator, such as LOS, since a marginal data input signal could cause intermittent toggling, leading to false alarm status. When it is anticipated that very low-level DIN signals will be encountered, the introduction of an adequate amount of LOS hysteresis is recommended to minimize any undesirable LOS signal toggling. Figure 7 illustrates a simple circuit that may be used to set a fixed level of Rev. 1.3 13 Si5023 LOS signal hysteresis for the Si5023 CDR. The value of R1 may be chosen to provide a range of hysteresis from 3 to 8 dB where a nominal value of 800 adjusts the hysteresis level to approximately 6 dB. Use a value of 500 or 1000 for R1 to provide 3 dB or 8 dB of hysteresis, respectively. Hysteresis is defined as the ratio of the LOS deassert level (LOSD) and the LOS assert level (LOSA). The hysteresis in decibels is calculated as 20log(LOSD/ LOSA). 4.9. Bit Error Rate (BER) Detection The Si5023 uses a proprietary Silicon Laboratories algorithm to generate a BER alarm on the BER_ALM pin and a BER indicator on the BERMON pin. The BERMON output is always enabled and functions as a dynamic analog level that is proportional to the detected bit error rate. This BERMON indicator can be used to monitor the quality and error status on the receive data input channel. The range of operation of the BER processor is between 1E-09 to 1E-03 as shown in Figures 8, 9, and 10. It is recommended that the BERMON output be filtered with an active low-pass filter configuration as shown in Figure 11. The external LPF may be followed by a voltage comparator or analog-to-digital converter where constant channel monitoring is desired. 40 mV LOS Threshold (mVPP) 30 mV LOS Disabled LOS Undefined 4.10. Data Slicing Level 40mV/V 10 mV max LOS Limited by Device Noise 15 mV 0 mV 0V 1.00 V 1.50 V 1.875 V 2.25 V 2.50 V LOS_LVL (V) Figure 6. LOS_LVL Mapping (PRBS23 Data) The Si5023 provides the ability to externally adjust the slicing level for applications that require BER optimization. Adjustments in slicing level of 25 mV (typical, relative to the internally-set input common mode voltage) are supported. The slicing level is set by applying a voltage between 0.75 V and 2.25 V to the SLICE_LVL input. See Figures 12 and 13 for the operation levels of the slice circuit. When SLICE_LVL is driven below 500 mV, the slicing level adjustment is disabled, and the slicing level is set to the cross-point of the differential input signal. Note: The slice circuit is designed to only work with pseudorandom, dc-balanced data. R1 3 LOS_LVL Si5023 CDR LOS 9 LOS Alarm Set LOS Level R2 10k 4.11. PLL Performance The PLL implementation used in the Si5023 is fullycompliant with the jitter specifications proposed for SONET/SDH equipment by Bellcore GR-253-CORE, Issue 3, September 2000 and ITU-T G.958. 4.11.1. Jitter Tolerance The Si5023's tolerance to input jitter exceeds that of the Bellcore/ITU mask shown in Figure 14. This mask defines the level of peak-to-peak sinusoidal jitter that must be tolerated when applied to the differential data input of the device. Note: There are no entries in the mask table for the data rate corresponding to OC-24 as that rate is not specified by either GR-253 or G.958. Figure 7. LOS Signal Hysteresis 14 Rev. 1.3 Si5023 0.900 0.800 0.84v to 0.87v max 0.700 0.600 BERMON (V) 0.500 0.400 0.300 0.200 0.100 0.000 Range of Operation -0.100 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 Bit Error Rate 1.E-04 1.E-03 1.E-02 1.E-01 Typical Limit Note: For Bit Error Rate < 1.E-09, BERMON (V) is < 0.4 V. Figure 8. Si5023 OC-48 BERMON Voltage Characteristics 0.900 0.800 0.84 to 0.87 V max 0.700 0.600 BERMON (V) 0.500 0.400 0.300 0.200 0.100 0.000 Range of Operation -0.100 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 Bit Error Rate 1.E-04 1.E-03 1.E-02 1.E-01 Typical Limit Note: For Bit Error Rate < 1.E-09, BERMON (V) is < 0.6 V. Figure 9. Si5023 GbE BERMON Voltage Characteristics Rev. 1.3 15 Si5023 0.900 0.800 0.84 to 0.87 V max 0.700 0.600 BERMON (V) 0.500 0.400 0.300 0.200 0.100 0.000 Range of Operation -0.100 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 Bit Error Rate 1.E-04 1.E-03 1.E-02 1.E-01 Typical Limit Note: For Bit Error Rate < 1.E-09, BERMON (V) is < 0.3 V. Figure 10. Si5023 OC-12/OC-3 BERMON Voltage Characteristics (Optional) Si5023 CDR BERMO N 6.8 F 13.7 k 5 k 1% 13.7 k 1Hz LPF Voltage Comparator 6.8 F BER Set Point *Note: See Table 9 (Si5023 Pin Descriptions) Figure 11. Si5023 BERMON Application Schematic 16 Rev. 1.3 Si5023 40 30 Not Specified Slice Disable 20 10 0 -10 -20 -30 -40 0.00 10 mV 10 mV Note: SLICE is a continuous curve. This chart shows the range of results from part-to-part. 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 Figure 12. OC-48 Slice Specification 25 20 15 10 Slice Disabled 10 mV 5 0 -5 -10 -15 -20 -25 0.00 Not Specified Upper Limit Typical 10 mV Note: SLICE is a continuous curve. This chart shows the range of results from part-to-part. Lower Limit 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 Figure 13. GbE, OC-12, and OC-3 Slice Specification Rev. 1.3 17 Si5023 Sinusoidal Input Jitter (UI PP ) 15 1.5 0.15 Si5023 typically generates less than 3.0 mUIrms of jitter when presented with jitter-free input data. Slope = 20 dB/Decade 4.12. RESET/DSPLL Calibration The Si5023 achieves optimal jitter performance by automatically calibrating the loop gain parameters within the DSPLL on powerup. Calibration may also be initiated by a high-to-low transition on the RESET/CAL pin. The RESET/CAL pin must be held high for at least 1 s. When RESET/CAL is released (set to low) the digital logic resets to a known initial condition, recalibrates the DSPLL, and will begin to lock to the incoming data stream. For a valid reset to occur when using Reference mode, a proper external reference clock frequency must be applied as specified in Table 8. f0 f1 f2 f3 Frequency ft SONET Data Rate OC-48 OC-12 OC-3 F0 (Hz) 10 10 10 F1 (Hz) 600 30 30 F2 F3 (kHz) (kHz) 6000 300 300 100 25 6.5 Ft (kHz) 1000 250 65 4.13. Clock Disable The Si5023 provides a clock disable pin (CLK_DSBL) that is used to disable the recovered clock output (CLKOUT). When the CLK_DSBL pin is asserted, the positive and negative terminals of CLKOUT are tied to VDD through 100 on-chip resistors. Figure 14. Jitter Tolerance Specification 4.11.2. Jitter Transfer The Si5023 exceeds all relevant Bellcore/ITU specifications related to SONET/SDH jitter transfer. Jitter transfer is defined as the ratio of output signal jitter to input signal jitter as a function of jitter frequency. (See Figure 15.) These measurements are made with an input test signal that is degraded with sinusoidal jitter whose magnitude is defined by the mask in Figure 15. Jitter Transfer 4.14. Data Squelch The Si5023 provides a data squelching pin (DSQLCH) that is used to set the recovered data output (DOUT) to binary zero. When the DSQLCH pin is asserted, the DOUT+ signal is held low (DOUT+ = 0) and the DOUT- signal is held high (DOUT- = 1). This pin can be is used to squelch corrupt data during LOS and LOL situations. Care must be taken when ac coupling these outputs; a long string of zeros or ones will not be held through ac coupling capacitors. 0.1 dB 20 dB/Decade Slope Acceptable Range 4.15. Device Grounding The Si5023 uses the GND pad on the bottom of the 28lead micro leaded package (QFN) for device ground. This pad should be connected directly to the analog supply ground. See Figure 21 on page 22 and Figure 22 on page 26 for the ground (GND) pad size and location. Fc Frequency 4.16. Bias Generation Circuitry SONET Data Rate OC-48 OC-12 OC-3 Fc (kHz) 2000 500 130 Figure 15. Jitter Transfer Specification 4.11.3. Jitter Generation The Si5023 exceeds all relevant specifications for jitter generation proposed for SONET/SDH equipment. The jitter generation specification defines the amount of jitter that may be present on the recovered clock and data outputs when a jitter free input signal is provided. The The Si5023 makes use of an external resistor to set internal bias currents. The external resistor allows precise generation of bias currents, which significantly reduces power consumption versus traditional implementations that use an internal resistor. The bias generation circuitry requires a 10 k (1%) resistor connected between REXT and GND. 18 Rev. 1.3 Si5023 4.17. Voltage Regulator The Si5023 regulates 2.5 V internally down from the external 3.3 V supply. Consumption is typically 170 mA. The Si5023 may accept control inputs as high as 3.6 V. 4.18. Differential Input Circuitry The Si5023 provides differential inputs for both the high-speed data (DIN) and the reference clock (REFCLK) inputs. Example terminations for these inputs are shown in Figures 16, 17, 18, and 19. In applications where direct dc coupling is possible, the 0.1 F capacitors may be omitted. (LOS operation is only guaranteed when ac coupled.) The data input limiting amplifier requires an input signal with a differential peak-to-peak voltage as specified in Table 2 on page 7 to ensure a BER of at least 10-12. The REFCLK input differential peak-to-peak voltage requirement is specified in Table 2. Clock source 2.5 k 0.1 F Zo = 50 RFCLK + 100 0.1 F Zo = 50 10 k 2.5 V (5%) 2.5 k RFCLK - 10 k GND Figure 16. Input Termination for REFCLK (ac coupled) TIA 2.5 V (5%) 0.1 F Zo = 50 DIN +, 50 5 k 0.1 F 50 Zo = 50 DIN -, 7.5 k GND Figure 17. Input Termination for DIN (ac coupled) Rev. 1.3 19 Si5023 Clock source 2.5 k 0.1 F Zo = 50 RFCLK + 10 k 50 RFCLK - 2.5 V (5%) 2.5 k 10 k 0.1 F GND Figure 18. Single-Ended Input Termination for REFCLK (ac coupled) Signal source 0.1 F Zo = 50 DIN +, 50 100 50 DIN-, 2.5 V (5%) 5 k 7.5 k 0.1 F GND Figure 19. Single-Ended Input Termination for DIN (ac coupled) 20 Rev. 1.3 Si5023 4.19. Differential Output Circuitry The Si5023 utilizes a CML architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with ac coupling is shown in Figure 20. In applications in which direct dc coupling is possible, the 0.1 F capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is specified in Table 2. VDD 2.5 V (5%) 100 50 DOUT+, CLKOUT+ 0.1 F Zo = 50 DOUT-, CLKOUT- 0.1 F Zo = 50 100 2.5 V (5%) 50 VDD Figure 20. Output Termination for DOUT and CLKOUT (ac coupled) Rev. 1.3 21 Si5023 5. Pin Descriptions: Si5023 BER_ALM CLKOUT+ 23 CLKDSBL BERMON 28 27 26 25 24 RATESEL0 RATESEL1 LOS_LVL SLICE_LVL REFCLK+ REFCLKLOL CLKOUT22 21 20 19 BER_LVL VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VDD REXT RESET/CAL VDD DOUT+ DOUTGND GND Pad 18 17 16 15 DIN+ VDD DIN- Top View Figure 21. Si5023 Pin Configuration Table 9. Si5023 Pin Descriptions Pin # 1,2 Pin Name RATESEL0, RATESEL1 I/O I Signal Level LVTTL Data Rate Select. These pins configure the onboard PLL for clock and data recovery at one of four user selectable data rates. See Table 7 for configuration settings. Notes: 1. These inputs have weak internal pullups. 2. After any change in RATESEL, the device must be reset. DSQLCH VDD LTR LOS Description 3 LOS_LVL I LOS Level Control. The LOS threshold is set by the input voltage level applied to this pin. Figure 6 on page 14 shows the input setting to output threshold mapping. LOS is disabled when the voltage applied is less than 1 V. 4 SLICE_LVL I Slicing Level Control. The slicing threshold level is set by applying a voltage to this pin as described in the Slicing Level section of the data sheet. If this pin is tied to GND, slicing level adjustment is disabled, and the slicing level is set to the midpoint of the differential input signal on DIN. Slicing level becomes active when the voltage applied to the pin is greater than 500 mV. 22 Rev. 1.3 Si5023 Table 9. Si5023 Pin Descriptions (Continued) Pin # 5 6 Pin Name REFCLK+ REFCLK- I/O I Signal Level See Table 2 Description Differential Reference Clock (Optional). When present, the reference clock sets the center operating frequency of the DSPLL for clock and data recovery. Tie REFCLK+ to VDD and REFCLK- to GND to operate without an external reference clock. See Table 8 for typical reference clock frequencies. O LVTTL Loss-of-Lock. This output is driven low when the recovered clock frequency deviates from the reference clock by the amount specified in Table 4 on page 9. If no external reference is supplied, this signal will be active when the internal PLL is no longer locked to the incoming data. 8 LTR I LVTTL Lock-to-Reference. When this pin is low, the DSPLL disregards the data inputs. If an external reference is supplied, the output clock is locked to the supplied reference. If no external reference is used, the DSPLL locks the control loop until LTR is released. Note: This input has a weak internal pullup. 7 LOL 9 LOS O LVTTL Loss-of-Signal. This output pin is driven low when the input signal is below the threshold set via LOS_LVL. (LOS operation is guaranteed only when ac coupling is used on the DIN inputs.) 10 DSQLCH LVTTL Data Squelch. When driven high, this pin forces the data present on DOUT+ = 0 and DOUT- = 1. For normal operation, this pin should be low. DSQLCH may be used during LOS/LOL conditions to prevent random data from being presented to the system. Note: This input has a weak internal pulldown. 11,14,18,21, 25 12 13 VDD DIN+ DIN- I 3.3 V See Table 2 Supply Voltage. Nominally 3.3 V. Differential Data Input. Clock and data are recovered from the differential signal present on these pins. AC coupling is recommended. 15 GND GND Production Test Input. This pin is used during production testing and must be tied to GND for normal operation. 16 17 DOUT- DOUT+ O CML Differential Data Output. The data output signal is a retimed version of the data recovered from the signal present on DIN. Rev. 1.3 23 Si5023 Table 9. Si5023 Pin Descriptions (Continued) Pin # 19 Pin Name RESET/CAL I/O I Signal Level LVTTL Reset/Calibrate. Driving this input high for at least 1 s will reset internal device circuitry. A high to low transition on this pin will force a DSPLL calibration. For normal operation, drive this pin low. Note: This input has a weak internal pulldown. Description 20 REXT External Bias Resistor. This resistor is used to establish internal bias currents within the device. This pin must be connected through a 10 k (1%) resistor to GND. 22 23 CLKOUT- CLKOUT+ O CML Differential Clock Output. The output clock is recovered from the data signal present on DIN except when LTR is asserted or the LOL state has been entered. 24 CLKDSBL I LVTTL Clock Disable. When this input is high, the CLKOUT output drivers are disabled. For normal operation, this pin should be low. Note: This input has a weak internal pulldown. 26 BER_LVL I Bit Error Rate Level Control. The BER threshold level is set by applying a voltage to this pin. The applied voltage is as described in the BER_LVL section. When the BER exceeds the programmed threshold, BER_ALM is driven low. If this pin is tied to GND, BER_ALM is disabled. 27 BER_ALM O LVTTL Bit Error Rate Alarm. This pin will be driven low to indicate that the BER threshold set by BER_LVL has been exceeded. There is no hysteresis. 28 BERMON O Bit Error Rate Monitor. The voltage on this pin is proportional to the detected bit error rate computed by the internal BER processor. This voltage output has a range of 0 to 0.87 V. See Figure 8 on page 15. The output is a current source, which requires a 5 k (1%) resistor to GND to guarantee the operating range shown in Figure 8. This pin may be left unconnected. GND Pad GND GND Supply Ground. Nominally 0.0 V. The 3 x 3 mm square GND pad found on the bottom of the 28-lead micro leaded package (see Figure 22) must be connected directly to supply ground. Minimize the ground path inductance for optimal performance. 24 Rev. 1.3 Si5023 6. Ordering Guide Part Number Si5023-X-GM Package 28-Lead QFN Voltage 3.3 Pb-Free Yes Temperature -40 to 85 C Notes: 1. "X" denotes product revision. 2. Add an "R" at the end of the device to denote tape and reel option; 2500 quantity per reel. 3. These devices use a NiPdAu pre-plated finish on the leads that is fully RoHS6 compliant while being fully compatible with both leaded and lead-free card assembly processes. 7. Top Mark Part Number Si5023 Die Revision--Device Type D-GM Assembly Date (YYWW) YY = Year WW = Work week Rev. 1.3 25 Si5023 8. Package Outline Figure 22 illustrates the package details for the Si5023. Table 10 lists the values for the dimensions shown in the illustration. For a pad layout recommendation please contact Silicon Laboratories. Figure 22. 28-Lead Quad Flat No-Lead (QFN) Table 10. Package Diagram Dimensions Controlling Dimension: mm Symbol Min A 0.80 A1 0.00 b 0.18 D D2 2.95 e E E2 2.95 L 0.50 0 aaa bbb ccc ddd eee Millimeters Nom 0.85 0.02 0.25 5.00 BSC 3.10 0.50 BSC 5.00 BSC 3.10 0.60 -- 0.10 0.10 0.08 0.10 0.05 Max 0.90 0.05 0.30 3.25 3.25 0.70 12 Notes: 1. 1.All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VHHD-1. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 26 Rev. 1.3 Si5023 DOCUMENT CHANGE LIST Revision 1.21 to Revision 1.22 Updated "3. Typical Application Schematic" on page 11. Updated Figure 11 on page 16. Updated Table 9 on page 22. Updated BERMON pin description. Revision 1.24 to Revision 1.25 Updated Table 2 on page 7. Added limits for VICM. Updated VOD. Updated Table 3 on page 8. Updated TCr-D. Updated TCf-D. Revised SLICE specification. Revision 1.22 to Revision 1.23 Updated Table 2 on page 7. Added "Output Common Mode Voltage (Si5023) (DOUT)" with updated values. Added "Output Common Mode Voltage (Si5023) (CLKOUT)" with updated values. Updated Table 4 on page 9. TAQ min/max values updated. Updated "4.8. Loss-of-Signal (LOS)" on page 13. Added note describing valid signal. Revised Figure 6, "LOS_LVL Mapping (PRBS23 Data)," on page 14, showing internal noise limits. Updated Table 3 on page 8. Added "Output Clock Duty Cycle OC-48/12/3" Updated "4.9. Bit Error Rate (BER) Detection" on page 14. Revised Figure 8. Added Figures 9 and 10. Updated Table 9 on page 22. Changed "clock input" to "DIN inputs" for Loss-of-Signal. Updated Figure 22, "28-Lead Quad Flat No-Lead (QFN)," on page 26. Updated Table 10, "Package Diagram Dimensions," on page 26. Changed dimension A. Changed dimension E2. Updated "4.10. Data Slicing Level" on page 14. Added Figures 12 and 13. Revised text. Updated pin description for RATESEL. Revision 1.25 to Revision 1.3 Added "7. Top Mark" on page 25. Updated "8. Package Outline" on page 26. Revision 1.23 to Revision 1.24 Removed all references to Si5022. Updated Table 2 on page 7. Idd Pd RIN +VICM +VOD +VOCM Updated Tables 3 and 4 on page 8. Clarified fCLK for the different settings of RATESEL Revised duty cycle, tCR-D, CTOL Revised slicing level accuracy Updated Table 8 on page 13. Removed OC3 support for 15/14 FEC Updated "4.17. Voltage Regulator" on page 19. Due to removal of Si5022 references Updated "6. Ordering Guide" on page 25. Added "X" to part number. 27 Rev. 1.3 Si5023 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 7801 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: HighSpeed@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 28 Rev. 1.3 |
Price & Availability of SI5023-EVB
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |